Current integrated circuit technology teaches three primary methods for making interconnections between an integrated circuit chip (a semiconductor die in which electronic circuitry is formed) and a substrate (a substrate routes electrical signals to and from the integrated circuit chip). These three methods of interconnection are wire-bonding, tape automated bonding (TAB), and Controlled Collapse Chip Connection (C4). Currently, wire-bonding interconnection is used in approximately 95% of packaged integrated circuits because wire-bonding is the least expensive of these methods and because commercially available programmable wire-bonding machines allow many different types of integrated circuit chips to be quickly and easily interconnected to a variety of package or substrate types.
However, wire-bonding has some disadvantages. For instance, with wire-bonding, bond wires are used to make the electrical connections between the chip bonding pads and the corresponding off-chip bonding contacts on a substrate Unfortunately, bond wires, like any other electrical conductors, have inherent inductances and capacitances. In particular, the cylindrical shape and long length of the bond wires result in relatively high inductances and capacitances. These high inductances and capacitances can create noise or cross-talk, i.e., undesirable electro-magnetic signals, on the intentional electrical signals traveling to and from the chip through the bond wires. Further, the generally long length of bond wires adds delay time to the propagation of electrical signals, slowing system performance.
Another disadvantage of wire-bonding is that the long bond wires typically extend in an arc from the bonding pads to the off-chip bonding contacts. As a result of this arcing, the minimum cross-sectional profile (or thickness) of a packaged integrated circuit using wire-bonding is relatively large compared to a packaged integrated circuit using the other, more expensive methods. Further, the bond wires must extend over the lateral distance between the chip bonding pads and the corresponding off-chip bonding contacts. As a result, wirebonding requires a longer interconnect area and the distance between chips mounted on a substrate of, for instance, a multi-chip module, must be greater than desired and the chips cannot be packed as densely.
Another problem with wire-bonding is the sensitivity to unintentional displacement of fragile bond wires during handling, or as a result of the process of encapsulating the chip. This phenomena is known in the art as bond wire sweep. Bond wire sweep can result in undesirable electrical shorting or cross-talk between adjacent bond wires causing circuit operation problems or circuit failure.
TAB partially overcomes the mechanical problems associated with wire bonding by eliminating bond wires and making direct electrical connection between the bonding pads on the chip and the inner ends of a set of electrically conductive leads that are formed on an electrically insulative tape. Thus, with TAB, bond wire sweep and large package profile are no longer problems; however, since leads are still used, an unacceptable level of cross-talk, noise and signal delay problems persist. In addition, with TAB, chip density in multi-chip modules is still relatively large. Finally, TAB is an expensive interconnection method which requires special metallurgy on the integrated circuit wafer and which requires complex mounting equipment to connect the tab leads to the substrate. As a result, TAB is often not an economically viable option.
C4 interconnection overcomes much of the problems associated with wire-bonding, including most of the noise and cross-talk problems, by eliminating bond wires. With C4, a more direct electrical connection between the bonding pads on the chip and the off-chip bonding contacts is made using specially processed integrated circuit chips and solder bump connections. However, since the solder forms weak bumps, the solder bumps must be nested at the center of the integrated circuit chip to minimize stress. This requires the metallized interconnection layers of the integrated circuit chip to be fanned-in to the bonding pads nested in the center of the integrated circuit chip. Correspondingly, the substrate leads must be fanned-in to the substrate contacts nested in the center of the substrate. This fan-in of the metallized interconnection layers of the integrated circuit chip and the substrate leads disadvantageously adds inductance to the integrated circuit chip and substrate, respectively.
In a typical C4 interconnection, the aluminum bonding pads on an integrated circuit chip are coated and patterned with successive layers of chromium, copper and gold. Next, solder bumps or balls are formed on the coated bonding pads. Flux, and sometimes solder paste, is applied to the substrate. Then the chip solder bumps are placed in contact with the substrate bonding contacts and heated to reflow the solder. The resulting solder joint is then cooled to form an electrically conductive connection between the chip and substrate. After cooling, the flux is washed away and the chips are inspected for flux residue. The solder used with conventional C4 processes can be problematic because many fluxes are corrosive and residual flux must be carefully cleaned off and the product thoroughly inspected.
In C4, the chromium, copper and gold form a diffusion/adhesion layer which performs several functions. One function is to protect the aluminum bonding pads from the corrosive effects of fluxes. Another function is to ensure that reliable contact can be made and maintained between the solder and the aluminum bonding pads during life of product since lead and tin do not readily solder to aluminum.
Finally, testing C4 bumped chips requires special expertise and equipment. This is in part because the C4 bumps located on the bonding pads are nested at the center of the integrated circuit chip and inserting test probes into the small nested area is very difficult. Also, since the testing of the C4 chips cannot be performed prior to the C4 bumping, chips processed for C4 interconnection must be processed and tested differently than chips processed for wire bonding interconnection and the equipment and expertise for C4 testing is not as widely available.
Nesting the substrate contacts to correspond with the nested C4 bumps also greatly complicates the substrate. In particular, to form the nested substrate contacts, substrates must be made with many more layers, very small vias, and fine patterning. This results in a very costly substrate material.
Thus, chips using C4 interconnection are processed more extensively using non-conventional technology, are more expensive, and are more sensitive to solder ball fatigue than chips using wire-bonding. Further, the substrates used with conventional C4 interconnections are more costly than substrates used with wire-bonding interconnections.
Another method of making an interconnection between an integrated circuit chip and substrate is presented in Gupta, U.S. Pat. No. 5,341,979 (hereinafter referred to as Gupta). Gupta teaches the formation of hourglass shaped gold bumps on bonding pads of an integrated circuit. The hourglass shaped gold bumps are matched with substrate contact pads and a bond is thermosonically formed between the hourglass shaped gold bumps and the contact pads.
Gupta teaches at column 7, lines 18 to 32, that, advantageously, the region of maximum stress of the hourglass shaped bumps is at the central or narrowest portion of the bump in contrast to conventional bumps where the region of maximum stress is at the interface of the bump and the semiconductor die or support substrate. However, Gupta teaches that to form the hourglass shaped bumps a relatively complex two layer photolithographic process must be used (see Gupta FIGS. 1 to 4 and related discussion).
What is needed is a method and apparatus for making the interconnection between an integrated circuit chip and a substrate that has the key advantages of C4, i.e., improved electrical performance, small package profile, and increased reliability, but which, at the same time, is relatively simple and inexpensive to implement and which enables use of less complex lower cost substrate materials. Further, a reliable interconnection should be made without the use of complex photolithographic processes.